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19-3502; Rev 3; 10/05
125V/2A, High-Speed, Half-Bridge MOSFET Drivers
General Description
The MAX5062/MAX5063/MAX5064 high-frequency, 125V half-bridge, n-channel MOSFET drivers drive highand low-side MOSFETs in high-voltage applications. These drivers are independently controlled and their 35ns typical propagation delay, from input to output, are matched to within 3ns (typ). The high-voltage operation with very low and matched propagation delay between drivers, and high source/sink current capabilities in a thermally enhanced package make these devices suitable for the high-power, high-frequency telecom power converters. The 125V maximum input voltage range provides plenty of margin over the 100V input transient requirement of telecom standards. A reliable on-chip bootstrap diode connected between VDD and BST eliminates the need for an external discrete diode. The MAX5062A/C and the MAX5063A/C offer both noninverting drivers (see the Selector Guide). The MAX5062B/D and the MAX5063B/D offer a noninverting high-side driver and an inverting low-side driver. The MAX5064A/B offer two inputs per driver that can be either inverting or noninverting. The MAX5062A/B/C/D and the MAX5064A feature CMOS (VDD / 2) logic inputs. www..com The MAX5063A/B/C/D and the MAX5064B feature TTL logic inputs. The MAX5064A/B include a break-beforemake adjustment input that sets the dead time between drivers from 16ns to 95ns. The drivers are available in the industry-standard 8-pin SO footprint and pin configuration, and a thermally enhanced 8-pin SO and 12-pin (4mm x 4mm) thin QFN packages. All devices operate over the -40C to +125C automotive temperature range.
Features
HIP2100/HIP2101 Pin Compatible (MAX5062A/ MAX5063A) Up to 125V Input Operation 8V to 12.6V VDD Input Voltage Range 2A Peak Source and Sink Current Drive Capability 35ns Typical Propagation Delay Guaranteed 8ns Propagation Delay Matching Between Drivers Programmable Break-Before-Make Timing (MAX5064) Up to 1MHz Combined Switching Frequency while Driving 100nC Gate Charge (MAX5064) Available in CMOS (VDD / 2) or TTL Logic-Level Inputs with Hysteresis Up to 15V Logic Inputs Independent of Input Voltage Low 2.5pF Input Capacitance Instant Turn-Off of Drivers During Fault or PWM Start-Stop Synchronization (MAX5064) Low 200A Supply Current Versions Available With Combination of Noninverting and Inverting Drivers (MAX5062B/D and MAX5063B/D) Available in 8-Pin SO, Thermally Enhanced SO, and 12-Pin Thin QFN Packages
MAX5062/MAX5063/MAX5064
Applications
Telecom Half-Bridge Power Supplies Two-Switch Forward Converters Full-Bridge Converters Active-Clamp Forward Converters Power-Supply Modules Motor Control
PART
Ordering Information
TEMP RANGE PINTOP PKG PACKAGE MARK CODE -- -- -- S8-5 S8-5 S8E-14
MAX5062AASA -40C to +125C 8 SO MAX5062BASA -40C to +125C 8 SO MAX5062CASA -40C to +125C 8 SO-EP*
MAX5062DASA -40C to +125C 8 SO-EP* -- S8E-14 *EP = Exposed paddle. Ordering Information continued at end of data sheet.
Selector Guide
PART MAX5062AASA MAX5062BASA MAX5062CASA MAX5062DASA HIGH-SIDE DRIVER Noninverting Noninverting Noninverting Noninverting LOW-SIDE DRIVER Noninverting Inverting Noninverting Inverting LOGIC LEVELS CMOS (VDD / 2) CMOS (VDD / 2) CMOS (VDD / 2) CMOS (VDD / 2) PIN COMPATIBLE HIP 2100IB -- -- --
Selector Guide continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.) VDD, IN_H, IN_L, IN_L+, IN_L-, IN_H+, IN_H-........-0.3V to +15V DL, BBM .....................................................-0.3V to (VDD + 0.3V) HS............................................................................-5V to +130V DH to HS.....................................................-0.3V to (VDD + 0.3V) BST to HS ...............................................................-0.3V to +15V dV/dt at HS ........................................................................50V/ns Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.9mW/C above +70C)...............470.6mW 8-Pin SO With Exposed Pad (derate 19.2mW/C above +70C)* ....................................................1538.5mW 12-Pin Thin QFN (derate 24.4mW/C above +70C)* ....................................................1951.2mW Maximum Junction Temperature .....................................+150C Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C *Per JEDEC 51 standard multilayer board.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VBST = +8V to +12.6V, VHS = GND = 0V, BBM = open, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = VBST = +12V and TA = +25C.) (Note 1)
PARAMETER POWER SUPPLIES Operating Supply Voltage VDD (Note 2) IN_H = IN_L = GND (no switching) MAX5062_/ MAX5063_ MAX5064_ VDD Operating Supply Current BST Quiescent Supply Current BST Operating Supply Current UVLO (VDD to GND) UVLO (BST to HS) UVLO Hysteresis LOGIC INPUT Input-Logic High VIH_ MAX5062_/MAX5064A, CMOS (VDD / 2) version MAX5063_/MAX5064B, TTL version Input-Logic Low VIL_ MAX5062_/MAX5064A, CMOS (VDD / 2) version MAX5063_/MAX5064B, TTL version Logic-Input Hysteresis VHYS MAX5062_/MAX5064A, CMOS (VDD / 2) version MAX5063_/MAX5064B, TTL version 0.67 x VDD 2 0.55 x VDD 1.65 0.4 x VDD 1.4 1.6 0.25 0.33 x VDD 0.8 V V V IDDO IBST IBSTO UVLOVDD UVLOBST fSW = 500kHz, VDD = +12V IN_H = IN_L = GND (no switching) fSW = 500kHz, VDD = VBST = +12V VDD rising BST rising 6.5 6.0 7.3 6.9 0.5 15 8.0 70 120 12.6 140 A 260 3 40 3 8.0 7.8 mA A mA V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD Quiescent Supply Current
IDD
2
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VBST = +8V to +12.6V, VHS = GND = 0V, BBM = open, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = VBST = +12V and TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS VIN_H+, VIN_L+ = 0V Logic-Input Current I_IN VIN_L = VDD for MAX5062B/D, MAX5063B/D VIN_H-, VIN_L-, VIN_H = VDD VIN_L = 0V for MAX5062A/C, MAX5063A/C IN_H+, IN_L+ IN_H, to GND Input Resistance RIN IN_L to VDD for MAX5062B/D, MAX5063B/D IN_H-, IN_L-, IN_H, to VDD IN_L for MAX5062A/C, MAX5063A/C to GND Input Capacitance HIGH-SIDE GATE DRIVER HS Maximum Voltage BST Maximum Voltage Driver Output Resistance (Sourcing) Driver Output Resistance (Sinking) DH Reverse Current (Latchup Protection) Power-Off Pulldown Clamp Voltage Peak Output Current (Sourcing) Peak Output Current (Sinking) LOW-SIDE GATE DRIVER Driver Output Resistance (Sourcing) Driver Output Resistance (Sinking) Reverse Current at DL (Latchup Protection) Power-Off Pulldown Clamp Voltage Peak Output Current (Sourcing) Peak Output Current (Sinking) INTERNAL BOOTSTRAP DIODE Forward Voltage Drop Turn-On and Turn-Off Time Vf tR IBST = 100mA IBST = 100mA 0.91 40 1.11 V ns IPK_LP IPK_LN RON_LP RON_LN VDD = 12V, IDL = 100mA (sourcing) VDD = 12V, IDL = 100mA (sinking) (Note 3) VDD = 0V or floating, IDL = 1mA (sinking) CL = 10nF, VDL = 0V CL = 10nF, VDL = 12V TA = +25C TA = +125C TA = +25C TA = +125C 400 0.95 2 2 1.16 2.5 3.5 2.1 3.2 3.3 4.6 2.8 4.2 mA V A A IDH_PEAK VHS_MAX VBST_MAX RON_HP RON_HN VDD = 12V, IDH = 100mA (sourcing) VDD = 12V, IDH = 100mA (sinking) (Note 3) VBST = 0V or floating, IDH = 1mA (sinking) CL = 10nF, VDH = 0V CL = 10nF, VDH = 12V TA = +25C TA = +125C TA = +25C TA = +125C 400 0.94 2 2 1.16 125 140 2.5 3.5 2.1 3.2 3.3 4.6 2.8 4.2 V V mA V A A CIN 2.5 pF 1 M -1 0.001 +1 A MIN TYP MAX UNITS
MAX5062/MAX5063/MAX5064
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VBST = +8V to +12.6V, VHS = GND = 0V, BBM = open, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = VBST = +12V and TA = +25C.) (Note 1)
PARAMETER SYMBOL CL = 1000pF Rise Time tR CL = 5000pF CL = 10,000pF CL = 1000pF Fall Time tF CL = 5000pF CL = 10,000pF Turn-On Propagation Delay Time Turn-Off Propagation Delay Time Delay Matching Between Inverting Input to Output and Noninverting Input to Output Delay Matching Between DriverLow and Driver-High Break-Before-Make Accuracy (MAX5064 Only) Internal Nonoverlap tD_ON tD_OFF Figure 1, CL = 1000pF (Note 3) Figure 1, CL = 1000pF (Note 3) CMOS TTL CMOS TTL CONDITIONS MIN TYP 7 33 65 7 33 65 30 35 30 35 2 55 63 55 63 8 ns ns ns ns MAX UNITS
SWITCHING CHARACTERISTICS FOR HIGH- AND LOW-SIDE DRIVERS (VDD = VBST = +12V)
tMATCH1
CL = 1000pF, BBM open for MAX5064, Figure 1 (Note 3) CL = 1000pF, BBM open for MAX5064, Figure 1 (Note 3) RBBM = 10k RBBM = 47k (Notes 3, 4) RBBM = 100k 40
ns
tMATCH2
2 16 56 95 1
8
ns
72
ns ns
Note 1: Note 2: Note 3: Note 4:
All devices are 100% tested at TA = +125C. Limits over temperature are guaranteed by design. Ensure that the VDD-to-GND or BST-to-HS voltage does not exceed 13.2V. Guaranteed by design, not production tested. Break-before-make time is calculated by tBBM = 8ns x (1 + RBBM / 10k).
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
Typical Operating Characteristics
(Typical values are at VDD = VBST = +12V and TA = +25C, unless otherwise specified.)
UNDERVOLTAGE LOCKOUT (VDD AND VBST RISING) vs. TEMPERATURE
MAX5062/3/4 toc01
VDD AND BST UNDERVOLTAGE LOCKOUT HYSTERESIS vs. TEMPERATURE
MAX5062/3/4 toc02
IDD vs. VDD
MAX5062/3/4 toc03
7.5 7.4 7.3 7.2 UVLO (V) 7.1 7.0 6.9 6.8 6.7 6.6 6.5 UVLOBST UVLOVDD
1.0 0.9 0.8 UVLO HYSTERESIS (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 UVLOVDD HYSTERESIS UVLOBST HYSTERESIS
MAX5064 IN_L-, IN_H- = VDD IN_L+, IN_H+ = GND 2V/div VDD
0V 500A/div 0A IDD
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
40s/div
IDDO + IBSTO vs. VDD (fSW = 250kHz)
3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
MAX5062/3/4 toc04
INTERNAL BST DIODE (I-V) CHARACTERISTICS
180 160 140 IDIODE (mA) 120 100 80 60 40 20 0 TA = +125C TA = +25C TA = 0C TA = -40C
MAX5062/3/4 toc05
200
IDDO + IBSTO (mA)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 VDD (V)
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VDD - VBST (V)
VDD QUIESCENT CURRENT vs. VDD (NO SWITCHING)
MAX5062/3/4 toc06
BST QUIESCENT CURRENT vs. BST VOLTAGE
18 15 IBST (A) 12 9 6 3 TA = -40C, TA = 0C, TA = +25C 0 TA = +125C VBST = VDD + 1V, NO SWITCHING
MAX5062/3/4 toc07
160 MAX5064 140 120 100 IDD (A) 80 60 TA = -40C 40 20 0 TA = +25C, TA = 0C TA = +125C
21
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VDD (V)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VBST (V)
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
Typical Operating Characteristics (continued)
(Typical values are at VDD = VBST = +12V and TA = +25C, unless otherwise specified.)
VDD AND BST OPERATING SUPPLY CURRENT vs. FREQUENCY
MAX5062/3/4 toc08
DH OR DL OUTPUT LOW VOLTAGE vs. TEMPERATURE
0.34 0.32 0.30 0.28 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 SINKING 100mA
MAX5062/3/4 toc09
10 9 8 IDDO + IBSTO (mA) 7 6 5 4 3 2 1 0 CL = 0
OUTPUT LOW VOLTAGE (V)
0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
PEAK DH AND DL SOURCE/SINK CURRENT
MAX5062/3/4 toc10
DH OR DL RISE TIME vs. TEMPERATURE (CL = 10nF)
108 96 DH OR DL tR (ns)
MAX5062/3/4 toc11 MAX5062/3/4 toc13
120 VDD = VBST = 8V
CL = 100nF
5V/div
84 72 60 48 36 24 12 0 VDD = VBST = 12V
2A/div
SINK AND SOURCE CURRENT
1s/div
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
DH OR DL FALL TIME vs. TEMPERATURE (CLOAD = 10nF)
110 100 90 80 tF (ns) 70 60 50 40 30 20 10 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) VDD = VBST = 12V VDD = VBST = 8V
MAX5062/3/4 toc12
DH OR DL RISE PROPAGATION DELAY vs. TEMPERATURE
60 55 50 PROPAGATION DELAY (ns) 45 40 35 30 25 20 15 10 5 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) DL DH
120
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers
Typical Operating Characteristics (continued)
(Typical values are at VDD = VBST = +12V and TA = +25C, unless otherwise specified.)
DH OR DL FALL PROPAGATION DELAY vs. TEMPERATURE
MAX5062/3/4 toc14
MAX5062/MAX5063/MAX5064
BREAK-BEFORE-MAKE DEAD TIME vs. RBBM
225 200 175 tBBM (ns) 150 125 100 75 50 25 0 MAX5064
MAX5062/3/4 toc15
60 55 50 PROPAGATION DELAY (ns) 45 40 35 30 25 20 15 10 5 0 DL DH
250
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
10
50
90
130
170
210
250 290
RBBM (k)
BREAK-BEFORE-MAKE DEAD TIME vs. TEMPERATURE
110 100 90 80 tBBM (ns) 70 60 50 40 30 20 10 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) RBBM = 10k 5V/div MAX5064 RBBM = 100k
MAX5062/3/4 toc16
DELAY MATCHING (DH/DL RISING)
MAX5062/3/4 toc17
120
CL = 0
5V/div
INPUT
DH/DL
10ns/div
DELAY MATCHING (DH/DL FALLING)
MAX5062/3/4 toc18
DH/DL RESPONSE TO VDD GLITCH
MAX5062/3/4 toc19
CL = 0
10V/div INPUT 10V/div
DH DL
5V/div
10V/div 5V/div DH/DL 5V/div
VDD
INPUT
10ns/div
40s/div
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
MAX5062/MAX5063 Pin Description
PIN 1 2 3 4 5 6 7 8 -- NAME VDD BST DH HS IN_H IN_L GND DL EP FUNCTION Power Input. Bypass to GND with a parallel combination of 0.1F and 1F ceramic capacitor. Boost Flying Capacitor Connection. Connect a 0.1F ceramic capacitor between BST and HS for the high-side MOSFET driver supply. High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate. Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver. High-Side Noninverting Logic Input Low-Side Noninverting Logic Input (MAX5062A/C, MAX5063A/C). Low-side inverting logic input (MAX5062B/D, MAX5063B/D). Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs. Low-Side-Gate Driver Output. Drives low-side MOSFET gate. Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground plane to aid in heat dissipation (MAX5062C/D, MAX5063C/D only).
MAX5064 Pin Description
PIN 1 2 3 4 NAME BST DH HS AGND FUNCTION Boost Flying Capacitor Connection. Connect a 0.1F ceramic capacitor between BST and HS for the high-side MOSFET driver supply. High-Side-Gate Driver Output. Drives high-side MOSFET gate. Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver. Analog Ground. Return path for low-switching current signals. IN_H/IN_L inputs referenced to Break-Before-Make Programming Resistor Connection. Connect a 10k to 100k resistor from BBM to AGND to program the break-before-make time (tBBM) from 16ns to 95ns. Resistance values greater than 200k disables the BBM function and makes tBBM = 1ns. Bypass this pin with at least a 1nF capacitor to AGND. High-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND when not used. High-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to VDD when not used. Low-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND when not used. Low-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to VDD when not used. Power Ground. Return path for high-switching current signals. Use PGND as a return path for the low-side driver. Low-Side-Gate Driver Output. Drives the low-side MOSFET gate. Power Input. Bypass to PGND with a 0.1F ceramic in parallel with a 1F ceramic capacitor. Exposed Pad. Internally connected to AGND. Externally connect to a large ground plane to aid in heat dissipation.
5
BBM
6 7 8 9 10 11 12 --
IN_HIN_H+ IN_LIN_L+ PGND DL VDD EP
8
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
IN_L+ VIH VIL
90% DL 10% tD_OFF1 tF IN_LVIH VIL tD_OFF2 tD_ON2 VIH VIL tD_ON1 tR
IN_H+
90% DH 10% tD_OFF3 tF IN_HVIH VIL tD_OFF4 tMATCH1 = (tD_ON2 - tD_ON1) or (tD_OFF2 - tD_OFF1) tMATCH2 = (tD_ON3 - tD_ON1) or (tD_ON4 - tD_ON2) or (tD_OFF3 - tD_OFF1) or (tD_OFF4 - tD_OFF2) tD_ON4 tD_ON3 tR
Figure 1. Timing Characteristics for Noninverting and Inverting Logic Inputs
Detailed Description
The MAX5062/MAX5063/MAX5064 are 125V/2A highspeed, half-bridge MOSFET drivers that operate from a supply voltage of +8V to +12.6V. The drivers are intended to drive a high-side switch without any isolation device like an optocoupler or drive transformer. The high-side driver is controlled by a TTL/CMOS logic signal referenced to ground. The 2A source and sink drive capability is achieved by using low RDS_ON pand n-channel driver output stages. The BiCMOS process allows extremely fast rise/fall times and low
propagation delays. The typical propagation delay from the logic-input signal to the drive output is 35ns with a matched propagation delay of 3ns typical. Matching these propagation delays is as important as the absolute value of the delay itself. The high 125V input voltage range allows plenty of margin above the 100V transient specification per telecom standards. The MAX5064 is available in a thermally enhanced TQFN package, which can dissipate up to 1.95W (at +70C) and allow up to 1MHz switching frequency while driving 100nC combined gate-charge MOSFETs.
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9
125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
Undervoltage Lockout
Both the high- and low-side drivers feature undervoltage lockout (UVLO). The low-side driver's UVLOLOW threshold is referenced to GND and pulls both driver outputs low when VDD falls below 6.8V. The high-side driver has its own undervoltage lockout threshold (UVLOHIGH), referenced to HS, and pulls DH low when BST falls below 6.4V with respect to HS. During turn-on, once VDD rises above its UVLO threshold, DL starts switching and follows the IN_L logic input. At this time, the bootstrap capacitor is not charged and the BST-to-HS voltage is below UVLOBST. For synchronous buck and half-bridge converter topologies, the bootstrap capacitor can charge up in one cycle and normal operation begins in a few microseconds after the BST-to-HS voltage exceeds UVLOBST. In the two-switch forward topology, the BST capacitor takes some time (a few hundred microseconds) to charge and increase its voltage above UVLOBST. The typical hysteresis for both UVLO thresholds is 0.5V. The bootstrap capacitor value should be selected carefully to avoid unintentional oscillations during turn-on and turn-off at the DH output. Choose the capacitor value about 20 times higher than the total gate capacitance of the MOSFET. Use a low-ESR-type X7R dielectric ceramic capacitor at BST (typically a 0.1F ceramic is adequate) and a parallel combination of 1F and 0.1F ceramic capacitors from V DD to GND (MAX5062_, MAX5063_) or to PGND (MAX5064_). The high-side MOSFET's continuous on-time is limited due to the charge loss from the high-side driver's quiescent current. The maximum on-time is dependent on the size of CBST, IBST (50A max), and UVLOBST. zero when in a low state. The driver RDS_ON is lower at higher VDD. Lower RDS_ON means higher source and sink currents and faster switching speeds.
Internal Bootstrap Diode
An internal diode connects from VDD to BST and is used in conjunction with a bootstrap capacitor externally connected between BST and HS. The diode charges the capacitor from VDD when the DL low-side switch is on and isolates VDD when HS is pulled high as the highside driver turns on (see the Typical Operating Circuit). The internal bootstrap diode has a typical forward voltage drop of 0.9V and has a 10ns typical turn-off/turn-on time. For lower voltage drops from VDD to BST, connect an external Schottky diode between VDD and BST.
Programmable Break-Before-Make (MAX5064)
Half-bridge and synchronous buck topologies require that the high- or low-side switch be turned off before the other switch is turned on to avoid shoot-through currents. Shoot-through occurs when both high- and low-side switches are on at the same time. This condition is caused by the mismatch in the propagation delay from IN_H/IN_L to DH/DL, driver output impedance, and the MOSFET gate capacitance. Shootthrough currents increase power dissipation, radiate EMI, and can be catastrophic, especially with high input voltages. The MAX5064 offers a break-before-make (BBM) feature that allows the adjustment of the delay from the input to the output of each driver. The propagation delay from the rising edges of IN_H and IN_L to the rising edges of DH and DL, respectively, can be programmed from 16ns to 95ns. Note that the BBM time (tBBM) has a higher percentage error at lower value because of the fixed comparator delay in the BBM block. The propagation delay mismatch (t MATCH_ ) needs to be included when calculating the total tBBM error. The low 8ns (maximum) delay mismatch reduces the total tBBM variation. Use the following equations to calculate R BBM for the required BBM time and tBBM_ERROR: t RBBM = 10k x BBM - 1 for RBBM < 200k 8ns tBBM _ ERROR = 0.15 x tBBM + tMATCH _ where tBBM is in nanoseconds.
Output Driver
The MAX5062/MAX5063/MAX5064 have low 2.5 RDS_ON p-channel and n-channel devices (totem pole) in the output stage. This allows for a fast turn-on and turn-off of the high gate-charge switching MOSFETs. The peak source and sink current is typically 2A. Propagation delays from the logic inputs to the driver outputs are matched to within 8ns. The internal p- and n-channel MOSFETs have a 1ns break-before-make logic to avoid any cross conduction between them. This internal break-before-make logic eliminates shootthrough currents reducing the operating supply current as well as the spikes at VDD. The DL voltage is approximately equal to VDD and the DH-to-HS voltage, a diode drop below VDD, when they are in a high state and to
10
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers
The voltage at BBM is regulated to 1.3V. The BBM circuit adjusts tBBM depending on the current drawn by RBBM. Bypass BBM to AGND with a 1nF or smaller ceramic capacitor (CBBM) to avoid any effect of ground bounce caused during switching. The charging time of CBBM does not affect tBBM at turn-on because the BBM voltage is stabilized before the UVLO clears the device turn-on. Topologies like the two-switch forward converter, where both high- and low-side switches are turned on and off simultaneously, can have the BBM function disabled by leaving BBM unconnected. When disabled, tBBM is typically 1ns.
Applications Information
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the MAX5062/MAX5063/MAX5064. Peak supply and output currents may exceed 4A when both drivers are driving large external capacitive loads in-phase. Supply drops and ground shifts create forms of negative feedback for inverters and may degrade the delay and transition times. Ground shifts due to insufficient device grounding may also disturb other circuits sharing the same AC ground return path. Any series inductance in the VDD, DH, DL, and/or GND paths can cause oscillations due to the very high di/dt when switching the MAX5062/ MAX5063/MAX5064 with any capacitive load. Place one or more 0.1F ceramic capacitors in parallel as close to the device as possible to bypass VDD to GND (MAX5062/MAX5063) or PGND (MAX5064). Use a ground plane to minimize ground return resistance and series inductance. Place the external MOSFET as close as possible to the MAX5062/MAX5063/MAX5064 to further minimize board inductance and AC path resistance. For the MAX5064_ the low-power logic ground (AGND) is separated from the high-power driver return (PGND). Apply the logic-input signal between IN_ to AGND and connect the load (MOSFET gate) between DL and PGND.
MAX5062/MAX5063/MAX5064
Driver Logic Inputs (IN_H, IN_L, IN_H+, IN_H-, IN_L+, IN_L-)
The MAX5062_/MAX5064A are CMOS (VDD / 2) logicinput drivers while the MAX5063_/MAX5064B have TTLcompatible logic inputs. The logic-input signals are independent of VDD. For example, the IC can be powered by a 10V supply while the logic inputs are provided from a 12V CMOS logic. Also, the logic inputs are protected against voltage spikes up to 15V, regardless of the VDD voltage. The TTL and CMOS logic inputs have 400mV and 1.6V hysteresis, respectively, to avoid double pulsing during transition. The logic inputs are high-impedance pins and should not be left floating. The low 2.5pF input capacitance reduces loading and increases switching speed. The noninverting inputs are pulled down to GND and the inverting inputs are pulled up to VDD internally using a 1M resistor. The PWM output from the controller must assume a proper state while powering up the device. With the logic inputs floating, the DH and DL outputs pull low as VDD rises up above the UVLO threshold. The MAX5064_ has two logic inputs per driver, which provide greater flexibility in controlling the MOSFET. Use IN_H+/IN_L+ for noninverting logic and IN_H-/ IN_L- for inverting logic operation. Connect IN_H+/IN_L+ to VDD and IN_H-/IN_L- to GND if not used. Alternatively, the unused input can be used as an ON/OFF function. Use IN_+ for active-low and IN_- for active-high shutdown logic.
Power Dissipation
Power dissipation in the MAX5062/MAX5063/MAX5064 is primarily due to power loss in the internal boost diode and the nMOS and pMOS FETS. For capacitive loads, the total power dissipation for the device is: PD = CL x VDD2 x fSW + (IDDO + IBSTO ) x VDD where CL is the combined capacitive load at DH and DL. VDD is the supply voltage and fSW is the switching frequency of the converter. PD includes the power dissipated in the internal bootstrap diode. The internal power dissipation reduces by PDIODE, if an external bootstrap Schottky diode is used. The power dissipation in the internal boost diode (when driving a capacitive load) will be the charge through the diode per switching period multiplied by the maximum diode forward voltage drop (Vf = 1V). PDIODE = CDH x (VDD - 1) x fSW x Vf
Table 1. MAX5064_ Truth Table
IN_H+/IN_L+ Low Low High High IN_H-/IN_LLow High Low High DH/DL Low Low High Low
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11
125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
The total power dissipation when using the internal boost diode will be PD and, when using an external Schottky diode, will be PD - PDIODE. The total power dissipated in the device must be kept below the maximum of 1.951W for the 12-pin TQFN package, 1.5W for the 8-pin SO with exposed pad, and 0.471W for the regular 8-pin SO package at TA = +70C ambient. * There are two AC current loops formed between the device and the gate of the MOSFET being driven. The MOSFET looks like a large capacitance from gate to source when the gate is being pulled low. The active current loop is from the MOSFET driver output (DL or DH) to the MOSFET gate, to the MOSFET source, and to the return terminal of the MOSFET driver (either GND or HS). When the gate of the MOSFET is being pulled high, the active current loop is from the MOSFET driver output, (DL or DH), to the MOSFET gate, to the MOSFET source, to the return terminal of the drivers decoupling capacitor, to the positive terminal of the decoupling capacitor, and to the supply connection of the MOSFET driver. The decoupling capacitor will be either the flying capacitor connected between BST and HS or the decoupling capacitor for VDD. Care must be taken to minimize the physical distance and the impedance of these AC current paths. * Solder the exposed pad of the TQFN (MAX5064) or SO (MAX5062C/D and MAX5063C/D) package to a large copper plane to achieve the rated power dissipation. Connect AGND and PGND at one point near VDD's decoupling capacitor return.
Layout Information
The MAX5062/MAX5063/MAX5064 drivers source and sink large currents to create very fast rise and fall edges at the gates of the switching MOSFETs. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Use the following PC board layout guidelines when designing with the MAX5062/MAX5063/MAX5064: * It is important that the VDD voltage (with respect to ground) or BST voltage (with respect to HS) does not exceed 13.2V. Voltage spikes higher than 13.2V from VDD to GND or BST to HS can damage the device. Place one or more low ESL 0.1F decoupling ceramic capacitors from V DD to GND (MAX5062/MAX5063) or to PGND (MAX5064), and from BST to HS as close as possible to the part. The ceramic decoupling capacitors should be at least 20 times the gate capacitance being driven.
12
______________________________________________________________________________________
125V/2A, High-Speed, Half-Bridge MOSFET Drivers
Typical Application Circuits
MAX5062/MAX5063/MAX5064
VDD = 8V TO 12.6V
VIN = 0 TO 125V
VDD
BST DH N
IN_H PWM CONTROLLER IN_L
MAX5062A/ MAX5063A
HS DL GND N
VOUT
PIN FOR PIN REPLACEMENT FOR THE HIP2100/HIP2101
Figure 2. MAX5062 Half-Bridge Conversion
VDD = 8V TO 12.6V CBST DH N
VIN = 0 TO 125V
VDD
BST
MAX5064
PWM IN_H+ HS IN_LBBM CBBM RBBM AGND PGND DL N VOUT
Figure 3. Synchronous Buck Converter
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13
125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
Typical Application Circuits (continued)
VDD = 8V TO 12.6V CBST VDD BST DH N VOUT VIN = 0 TO 125V
MAX5064
PWM IN_H+ HS
IN_L+
BBM AGND PGND
DL
N
Figure 4. Two-Switch Forward Conversion
VDD = 8V TO 12.6V CBST DH N
VIN = 0 TO 125V
VDD PWM IN_H+
BST
MAX5064_
IN_LBBM CBBM RBBM AGND PGND
HS DL N
VOUT
Figure 5. MAX5064 Half-Bridge Converter
14
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125V/2A, High-Speed, Half-Bridge MOSFET Drivers
Functional Diagrams
MAX5062/MAX5063/MAX5064
MAX5062A MAX5062C
VDD/2 CMOS BST 2 5 IN_H DH 3 5 IN_H
MAX5062B/ MAX5062D
VDD/2 CMOS BST 2 DH 3 5 IN_H
MAX5063A/ MAX5063C
TTL BST 2 DH 3
HS 4 VDD 1 6 IN_L DL 8 GND 7 SO/SO-EP SO/SO-EP 6 IN_L
HS 4 VDD 1 DL 8 GND 7 SO/SO-EP 6 IN_L
HS 4 VDD 1 DL 8 GND 7
MAX5063B/ MAX5063D
TTL BST 2 5 IN_H DH 7 3 6 5 9 8 GND 7 SO/SO-EP 4 IN_H+ IN_HBBM IN_L+ IN_LAGND
MAX5064A
VDD/2 CMOS BST 1 DH 7 2 6 5 9 8 PGND 10 THIN QFN 4 IN_H+ IN_HBBM IN_L+ IN_LAGND
MAX5064B
TTL BST 1 DH 2
HS 4 VDD 1 6 IN_L DL 8
HS 3 VDD 12 DL 11
HS 3 VDD 12 DL 11 PGND 10 THIN QFN
Pin Configurations
TOP VIEW
IN_L+ 9 VDD BST DH 1 2 3 8 7 DL GND IN_L IN_H VDD BST DH 1 2 3 8 7 DL GND DL 11 6 5 IN_L IN_H VDD 12 IN_L- IN_H+ 8 7
PGND 10
6 5 4
IN_HBBM AGND
MAX5062A/B MAX5063A/B
6 5
MAX5062C/D MAX5063C/D
MAX5064A/ MAX5064B
HS 4
HS 4
SO
SO-EP
1 BST
2 DH
3 HS
THIN QFN
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15
125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
Typical Operating Circuit
VIN = 125V VDD 8V TO 12.6V
MAX5064A/ MAX5064B
BST PWM IN IN_H+ DH IN_HHS VDD IN_L+ DL VDD IN_LBBM AGND RBBM CBBM PGND CDD VOUT CBST
Selector Guide (continued)
PART MAX5063AASA MAX5063BASA MAX5063CASA MAX5063DASA MAX5064AATC MAX5064BATC HIGH-SIDE DRIVER Noninverting Noninverting Noninverting Noninverting Both Inverting and Noninverting Both Inverting and Noninverting LOW-SIDE DRIVER Noninverting Inverting Noninverting Inverting Both Inverting and Noninverting Both Inverting and Noninverting LOGIC LEVELS TTL TTL TTL TTL CMOS (VDD / 2) TTL PIN COMPATIBLE HIP2101IB -- -- -- -- --
Ordering Information (continued)
PART MAX5063AASA MAX5063BASA MAX5063CASA MAX5063DASA MAX5064AATC MAX5064BATC TEMP RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C PINPACKAGE 8 SO 8 SO 8 SO-EP* 8 SO-EP* 12 TQFN 12 TQFN TOP MARK -- -- -- -- AAEF AAEG PKG CODE S8-5 S8-5 S8E-14 S8E-14 T1244-4 T1244-4
Chip Information
TRANSISTOR COUNT: 790 PROCESS: HV BiCMOS
*EP = Exposed paddle. 16 ______________________________________________________________________________________
125V/2A, High-Speed, Half-Bridge MOSFET Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
8L, SOIC EXP. PAD.EPS
MAX5062/MAX5063/MAX5064
PACKAGE OUTLINE 8L SOIC, .150" EXPOSED PAD
21-0111
B
1
1
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17
125V/2A, High-Speed, Half-Bridge MOSFET Drivers MAX5062/MAX5063/MAX5064
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1
2
18
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24L QFN THIN.EPS
125V/2A, High-Speed, Half-Bridge MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5062/MAX5063/MAX5064
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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